A variety of semiconductor-based dynamic random-access memory devices are known and/or commercially available. The above-referenced '154, '890, '582, '972, and '766 applications and '481, '342, '248, '241, '326, '763, and '765 patents each relate to and describe in some detail how various aspects of semiconductor memory device technology have been and will continue to be crucial to the continued progress in the field of computing in general, and to the accessibility to and applicability of computer technology in particular.
Advances in the field of physical and structural aspects of semiconductor technology, for example various developments which have reduced the minimum practical size of semiconductor structures to well within the sub-micron range, have proven greatly beneficial in increasing the speed, capacity and/or capability of state-of-the-art semiconductor devices. Notwithstanding such advances, however, certain logical and algorithmical considerations must still be addressed.
In fact, some advances in semiconductor processing technology in some sense make it particularly important, in some cases imperative, that certain logical or algorithmical compensatory measures be taken in the designing of semiconductor devices.
For designers and manufacturers of semiconductor devices in general, and for semiconductor memory devices in particular, there are numerous considerations which must be addressed. Certain aspects of semiconductor memory design become even more critical as their speed and density is increased and their size is decreased. The present invention is directed to a memory device in which various design considerations are taken into account in such a manner as to yield numerous beneficial results, including speed and density maximization, size and power consumption minimization, enhanced reliability, and improved yield, among others.
Memory integrated circuits (ICs) have a memory array of millions of memory cells used to store electrical charges indicative of binary data. The presence of an electrical charge in a memory cell typically equates to a binary "1" value and the absence of an electrical charge typically equates to a binary "0" value. The memory cells are accessed via address signals on row and column lines. Once accessed, data is written to or read from the addressed memory cell via digit or bit lines. One important consideration in the design of semiconductor memory devices relates to the arrangement of memory cells, row lines, and column lines in a particular layout or configuration, commonly referred to as the device's "topology". Circuit topologies vary considerably among variously designed memory ICs.
One common design found in many memory circuit topologies is the "folded bit line" structure. In a folded bit line construction, the bit lines are arranged in pairs with each pair being assigned to complementary binary signals. For example, one bit line in the pair is dedicated to a binary signal DATA and the other bit line is dedicated to handle the complementary binary signal DATA*. (The asterisk notation "*" is used throughout this disclosure to indicate the binary complement of a signal or data value.)
The memory cells are connected to either of the bit lines in the folded pair. During read and write operations, the bit lines are driven to opposing voltage levels depending upon the data content being written to or read from the memory cell. The following example describes a read operation of a memory cell holding a charge indicative of a binary `1": The voltage potential of both bit lines in the pair is first equalized to a middle voltage level, for example, 2.5 volts. Then, the addressed memory cell is accessed and the charge held therein is transferred to one of the bit lines, raising the voltage of that bit line slightly above that line's counterpart in the pair. A sense amplifier, or similar circuit, senses the voltage differential on the bit line pair and further increases this differential by increasing the voltage on the first bit line to, say, 5 volts, and decreasing the voltage on the second bit line to, say, 0 volts. The folded bit lines thereby output the data in complementary form.
One variation on the folded bit line structure is a so-called "twisted" bit line structure. FIG. 1 illustrates a twisted bit line structure having bit line pairs D0/D0* through D3/D3* that flip or twist at junctions 1 across the array. Memory cells are coupled to the bit line pairs throughout the array. Representative memory cells 2a through 2n and 3a through 3n are represented in FIG. 1 coupled to bit line pair D0/D0*. The twisted bit line structure evolved as a technique to reduce bit-line interference noise during chip operation. Such noise is increasingly more problematic as memory capacities increase and the sizes of physical structures on the chip decrease. The twisted bit line structure is therefore particularly advantageous in larger memories, such as a 64 megabit (Mbit) or larger dynamic random access memory (DRAM).
A twisted bit line structure presents a more complex topology than the simple folded bit line construction. Addressing memory cells in the FIG. 1 layout is more involved. For instance, different addresses are used for the memory cells on either side of a twist junction 1. As memory ICs increase in memory capacity, yet stay the same or decrease in size, noise problems and other layout constraints force the designer to conceive of more intricate configurations. As a result, the topologies of these circuits become more and more complex, and are more difficult to describe mathematically as each layer of complexity adds additional terms to a topology-describing equation. This in turn may give rise to more complex addressing schemes.
One problem that arises for memory ICs involves testing procedures. It is increasingly more difficult to test memory ICs that have intricate topologies. To test ICs, memory manufacturers often employ a testing machine that is preprogrammed with a complex boolean function that describes the topology of the memory IC. Conventional testing machines are capable of handling limited-sized addresses (e.g., 6-bits). As topologies grow more complex, however, such addresses may be incapable of fully addressing all individual cells for some test patterns. This renders the testing apparatus ineffective. Furthermore, if a user wishes to troubleshoot a particular memory device after some period of use, it is very difficult to derive the necessary boolean function for input to the testing machine without consulting the manufacturer.
The difficulties associated with memory IC testing become more manifest when a form of compression is used during testing to accelerate the testing period. It is common to write test patterns of all "1"s or all "0"s to a group of memory cells simultaneously. Consider the following example test pattern of writing all "1"s to the memory cells in the twisted bit line pairs of FIG. 1. Under the testing compression, one bit is used to address four bit line pairs D0/D0*, D1/D1*, D2/D2*, and D3/D3. Under conventional addressing schemes, the task of placing "1's in all memory cells is impossible because it cannot be discerned from a single address whether the memory cell, in order to receive a "1", needs to have a binary "1" or "0" placed on the bit line connected to the memory cell. Accordingly, testing machines may not adequately test memory ICs of complex topologies. Conversely, it is less desirable to test memory ICs on a per-cell basis, as the necessary testing period is too long.
Another consideration which must be taken into account in the design of memory ICs arises, as noted above, as a result of the extremely small size of various components (transistors, diodes, etc . . . ) disposed on a single chip, which renders the chip susceptible to component defects caused, for example, by material impurities and fabrication hazards. In order to address such this problems, chips are often built with redundant components and/or circuits that can be switched-in in lieu of corresponding circuits found defective during testing or operation. Usually the switching-out of a defective component or circuit and the switching-in of a corresponding redundant element is accomplished by using programmable logic circuits which are activated by blowing certain fuse-type devices built into the chip's circuitry. The blowing of the fuse-type devices is normally performed prior to packaging, burn-in and delivery of the IC die.
The number of redundant circuits available in a given IC is of course limited by the space available on the chip. Allocation of IC area is balanced between the competing goals of providing the maximum amount of primary circuitry, while maintaining adequate redundancy.
Memory chips are particularly well suited to benefit from redundancy systems, since typical memory ICs comprise millions of essentially equivalent memory cells, each of which capable of storing a logical 1 or 0 value. The cells are typically divided into generally autonomous "sections" or memory "arrays". For example, in a 16 Mbit DRAM there may be 4 sections of 4 Mbits apiece. The memory cells are typically arranged into an array of rows and columns, with a single row or column being referred to herein as an "element.". A number of elements may be grouped together to form a "bank" of elements.
Over the years, engineers have developed many redundancy schemes which strive to efficiently use the available space on an IC. One recent scheme proposed by Morgan (U.S. Pat. No. 5,281,868) exploits the fact that fabrication defects typically corrupt physically adjacent memory locations. The scheme proposed in the Morgan '868 patent reduces the number of fuses required to replace two adjacent columns by using one set of column-determining fuses to address the defective primary column, and an incrementor for addressing an adjacent column. A potential problem with this scheme, however, is that sometimes only one column is defective. Thus, more columns may be switched-out than is necessary to circumvent the defect.
Another perceived problem with common redundancy systems is that redundant elements serving one SAB may not be available for use by other SABs. Providing this capability using conventional techniques results in a prohibitive number of interconnection lines and switches. Because the redundant circuitry located on each SAB may only be available to replace primary circuitry on that SAB, each SAB must have an adequate number of redundant circuits available to replace the most probable number of defective primary circuits which may occur. Often, however, one SAB will have no defects, while another has more defects than can be replaced by its redundant circuitry. In the SAB with no defects, the redundant circuitry will be unused while still taking up valuable space. The SAB having too many defects may cause the entire chip to be scrapped.
While providing redundant elements in a semiconductor memory is effective in facilitating the salvage of a device having some limited number of defects in its memory array, certain other types of defects can cause the device to exhibit undesirable characteristics such as increased standby current, speed degradation, reduction in operating temperature range, or reduction in supply voltage range. Certain of these types of defects cannot be repaired effectively through redundancy techniques. Defects such as power-to-ground shorts in a portion of the array can prevent the device from operating even to the extent required to locate the defect in a test environment. Memory devices with limited known defects have been sold as "partials", "audio RAMs" or "off spec devices" provided that the defects do not prohibitively degrade the performance of the functional portions of the memory. The value of a partially functional device decreases dramatically as the performance of the device deviates from that of the standard fully-functional device. The desire to make use of devices with limited defects, and the problems associated with the performance of these devices due to the defects are well known in the industry.
The concept of providing redundant circuitry within a memory device addresses a problem that is essentially physical in nature, and, as noted above, involves a trade-off in the allocation of chip area between primary and redundant elements. The aforementioned issue of device topology, on the other hand, provides a good illustration of a consideration which has both physical (electrical) and logical significance, since the twisted bit-line arrangement complicates the task of testing the device. Another example of a consideration which has both structural and logical impact involves the manner in which memory locations within a memory device are accessed.
Fast page mode DRAMs are among the most popular standard semiconductor memories today. In DRAMs supporting fast page mode operation, a row address strobe signal (/RAS) is used to latch a row address portion of a multiplexed DRAM address. Multiple occurrences of a column address strobe signal (/CAS) are then used to latch multiple column addresses to access data within the selected row. On the falling edge of /CAS an address is latched, and the DRAM outputs are enabled. When /CAS transitions high the DRAM outputs are placed in a high-impedance state (tri-state). With advances in the production of integrated circuits, the internal circuitry of the DRAM operates faster than ever. This high speed circuitry has allowed for faster page mode cycle times. A problem exists in the reading of a DRAM when the device is operated with minimum fast page mode cycle times. /CAS may be low for as little as 15 nanoseconds, and the data access time from /CAS to valid output data (tCAC) may be up to 15 nanoseconds; therefore, in a worst case scenario there is no time to latch the output data external to the memory device. For devices that operate faster than the specifications require, the data may still only be valid for a few nanoseconds.
Those of ordinary skill in the art will appreciate that on a heavily loaded microprocessor memory bus, trying to latch an asynchronous signal that is valid for only a few nanoseconds can be very difficult. Even providing a new address every 35 nanoseconds requires large address drivers which create significant amounts of electrical noise within the system. To increase the data throughput of a memory system, it has been common practice to place multiple devices on a common bus. For example, two fast page mode DRAMs may be connected to common address and data buses. One DRAM stores data for odd addresses, and the other for even addresses. The /CAS signal for the odd addresses is turned off (high) when the /CAS signal for the even addresses is turned on (low). This so-called "interleaved" memory system provides data access at twice the rate of either device alone. If the first /CAS is low for 20 nanoseconds and then high for 20 nanoseconds while the second /CAS goes low, data can be accessed every 20 nanoseconds (i.e., at a rate of 50 megahertz). If the access time from /CAS to data valid is fifteen nanoseconds, the data will be valid for only five nanoseconds at the end of each 20 nanosecond period when both devices are operating in fast page mode. As cycle times are shortened, the data valid period goes to zero.
There is a demand for faster, higher density, random access memory integrated circuits which provide a strategy for integration into today's personal computer systems. In an effort to meet this demand, numerous alternatives to the standard DRAM architecture have been proposed. One method of providing a longer period of time when data is valid at the outputs of a DRAM without increasing the fast page mode cycle time is called Extended Data Out (EDO) mode. In an EDO DRAM the data lines are not tri-stated between read cycles in a fast page mode operation. Instead, data is held valid after /CAS goes high until sometime after the next /CAS low pulse occurs, or until /RAS or the output enable (/OE) goes high. Determining when valid data will arrive at the outputs of a fast page mode or EDO DRAM can be a complex function of when the column address inputs are valid, when /CAS falls, the state of /OE and when /CAS rose in the previous cycle. The period during which data is valid with respect to the control line signals (especially /CAS) is determined by the specific implementation of the EDO mode, as adopted by various DRAM manufacturers.
Methods to shorten memory access cycles tend to require additional circuitry, additional control pins and nonstandard device pinouts. The proposed industry standard synchronous DRAM (SDRAM), for example, has an additional pin for receiving a system clock signal. Since the system clock is connected to each device in a memory system, it is highly loaded, and it is always toggling circuitry in every device. SDRAMs also have a clock enable pin, a chip select pin and a data mask pin. Other signals which appear to be similar in name to those found on standard DRAMs have dramatically different functionality on a SDRAM. The addition of several control pins has required a deviation in device pinout from standard DRAMs which further complicates design efforts to utilize these new devices. Significant amounts of additional circuitry are required in the SDRAM devices which in turn result in higher device manufacturing costs.
In order for existing computer systems to use an improved device having a nonstandard pinout, those systems must be extensively modified. Additionally, existing computer system memory architectures are designed such that control and address signals may not be able to switch at the frequencies required to operate the new memory device at high speed due to large capacitive loads on the signal lines. The Single In-Line Memory Module (SIMM) provides an example of what has become an industry standard form of packaging memory in a computer system. On a SIMM, all address lines connect to all DRAMs. Further, the row address strobe (/RAS) and the write enable (/WE) are often connected to each DRAM on the SIMM. These lines inherently have high capacitive loads as a result of the number of device inputs driven by them. SIMM devices also typically ground the output enable (/OE) pin making /OE a less attractive candidate for providing extended functionality to the memory devices.
There is a great degree of resistance to any proposed deviations from the standard SIMM design due to the vast number of computers which use SIMMs. Industry's resistance to radical deviations from standards, and the inability of current systems to accommodate the new memory devices tend to delay the widespread acceptance of non-standard parts. Therefore, only limited quantities of devices with radically different architectures will be manufactured initially. This limited manufacture prevents the reduction in cost which typically can be accomplished through the manufacturing improvements and efficiencies associated with a high volume product.
There is another perceived difficulty associated with performing write cycles at increasingly high frequencies. In a standard DRAM, write cycles are performed in response to both /CAS and /WE being low after /RAS is low. Data to be written is latched, and the write cycle begins when the latter of /CAS and /WE goes low. In order to allow for maximum "page mode" operating frequencies, the write cycle is often timed out, so that it can continue for a short period of time after /CAS goes high, especially for "late write" cycles. Maintaining the write cycle throughout the timeout period eases the timing specifications for /CAS and /WE that the device user must meet, and reduces susceptibility to glitches on the control lines during a write cycle. The write cycle is terminated after the timeout period, and if /WE is high a read access begins based on the address present on the address input lines. The read access will typically begin prior to the next /CAS falling edge so that the column address to data valid specification can be met (tAA). In order to begin the read cycle as soon as possible, it is desirable to minimize write cycle time while guaranteeing completion of the write cycle. Minimizing the write cycle duration in turn minimizes the margin to some device operating parameters despite the speed at which the device is actually used. Circuits to model the time required to complete the write cycle typically provide an estimate of the time required to write an average memory cell. While it is desirable to minimize the write cycle time, it is also necessary to guarantee that enough time is allowed for the write to complete, so extra delay may be added, making the write cycle slightly longer than required.
Throughout a memory device's product lifetime, manufacturing process advances and circuit enhancements often allow for increases in device operating frequencies. Write cycle timing circuits may need to be adjusted to shorten the minimum write cycle times to match these performance improvements. Fine tuning of these timing circuits is time consuming and costly. If the write cycles are too short, the device may fail under some or all operating conditions. If the write cycles are too long, the device may not be able to achieve the higher operating frequencies that are more profitable for the device manufacturers.
A further consideration to be addressed in the design of semiconductor devices that has both process and algorithmic significant relates to the relative physical locations of the various functional components on a given IC. Those of ordinary skill in the art will appreciate, for example, that including larger numbers of metallic or otherwise conductive layers within the allowable design parameters (so-called "design rules) of a particular species of semiconductor device can simplify, reduce, or mitigate certain logical hurdles. However, inclusion of more metal layers tends to increase the cost and complexity of the manufacturing process. Thus, while conventional wisdom may suggest grouping or locating particular elements of a semiconductor device in a certain area for algorithmic and/or logical reasons, such approaches may not be entirely optimal when viewed from the perspective of manufacturing and processing considerations.
Yet another consideration to be addressed in the design of semiconductor devices relates to the power supply circuitry for such devices. The design of systems which incorporate semiconductor devices such as microprocessors, memories, etc. . . is routinely constrained by a limited number of power supply voltages (V.sub.cc). For example, consider a portable computer system powered by a conventional battery having a limited power supply voltage. For proper operation, different components of the system, such as a display, a processor, and memory employ several technologies which require power to be supplied at various operating voltages. Components often require operating voltages of a greater magnitude than the power supply voltage or in other cases involve a voltage of reverse polarity. The design of a system, therefore, includes power conversion circuitry to efficiently develop the required operating voltages. One such power conversion circuit is known as a charge pump.
The demand for highly-efficient and reliable charge pump circuits has increased with the increasing number of applications utilizing battery powered systems such as notebook computers, portable telephones, security devices, battery backed data storage devices, remote controls, instrumentation, and patient monitors, to name a few.
Inefficiencies in conventional charge pumps lead to reduced system capability and lower system performance in both battery and non-battery operated systems. Inefficiency can adversely affect system capabilities causing limited battery life, excess heat generation, and high operating costs. Examples of lower system performance include low speed operation, excessive delays in operation, loss of data, limited communication range, and the inability to operate over wide variations in ambient conditions including ambient light level and temperature.
Product reliability is a product's ability to function within given performance limits, under specified operating conditions over time. "Infant mortality" is the failure of an integrated circuit (IC) early in its life due to manufacturing defects. Limited reliability of a charge pump can affect the reliability of the entire system.
To reduce infant mortality, new batches of semiconductor IC devices (e.g., charge pumps) are "burned-in" before being shipped to customers. Burn-in is a process designed to accelerate the occurrence of those failures which are commonly at fault for infant mortality. During the burn-in process, the ICs are dynamically stressed at high temperature (e.g., 125.degree. C.) and higher-than-normal voltage (for example, 7 volts for a 5 volt device) in cycles that can last several hours or days. The devices can be tested for functionality before, after, and even during the burn-in cycles. Those devices that fail are eliminated.
Conventional pump circuits are characterized by a two part cycle of operation and low duty cycle. Pump operation includes pumping and resetting. Duty cycle is low when pumping occurs at less than 50% of the cycle. Low duty cycle Consequently introduces low frequency components into the output DC voltage provided by the pump circuit. Low frequency components cause interference between portions of a system, intermittent failures, and reduced system reliability. Some systems employed conventional pump circuits include filtering circuits at additional cost, circuits to operate the pump at elevated frequency, or both. Elevated frequency operation in some cases leads to increased system power dissipation with attendant adverse effects.
During normal operation of a charge pump, especially charge pumps providing operating voltages higher than V.sub.cc (boosted voltages), certain internal "high-voltage" nodes in the charge pump circuitry reach voltages having a magnitude significantly higher than either the power-supply voltage or the produced operating voltage (so-called "over-voltages"). These over-voltages can reach even higher levels under the dynamic stress high voltages during burn-in testing. When an IC charge pump is tested during a burn-in cycle, high burn-in over-voltages in combination with high burn-in temperatures can cause oxidation of silicon layers of the IC device and can permanently damage the charge pump.
In addition to constraints on the number of power supply voltages available for system design, there is an increasing demand for reducing the magnitude of the power supply voltage. The demand in diverse applications areas could be met with high efficiency charge pumps that operate from a supply voltage of less than 5 volts.
Such applications include memory systems backed by 3 volt standby supplies, processors and other integrated circuits that require either reverse polarity substrate biasing or booted voltages outside the range 0 to 3 volts for improved operation. As supply voltage is reduced, further reduction in the size of switching components paves the way for new and more sophisticated applications. Consequently, the need for high efficiency charge pumps is increased because voltages necessary for portions of integrated circuits and other system components are more likely to be outside a smaller range.